In digital communication systems, often a clock signal (or just "clock") must be recovered from a data signal in the receiver. Ideally, signal level transitions in the data signal are equally or regularly spaced, with a period determined by the bit rate of the signal. In real world applications, however, when a data stream arrives at the receiver, the period of successive bits may be slightly longer or shorter than the period defined by the bit rate of the given signal. This variability may be referred to as "jitter".
Commonly, filtering jitter from a clock signal makes use of a phase locked loop (PLL). A typical PLL filter includes a variable frequency signal source, a loop filter and a phase difference detector. In operation, a reference clock (the clock to be filtered) is compared, at the phase difference detector, to a signal output from the signal source. An indication of the phase difference detected between the signal source output and the reference clock is received by the loop filter and a filtered indication is passed to the signal source. Based on the filtered indication, the frequency of the signal output from signal source is adjusted. This adjustment acts to reduce the phase difference. After a "training" period, the resulting signal at the output of the signal source achieves a lock on the frequency and phase of the reference clock signal, and has qualities (i.e. low jitter) of the variable frequency signal source.
Often filters are described by a dynamic response. A desired dynamic response for a PLL may be attained by setting loop filter parameters appropriately. Bandwidth and damping factor are often the loop filter parameters that are set by a filter designer. The choice of these parameters depends upon the application. A wide bandwidth and low damping factor are desired to track a reference clock tightly (and therefore tolerate jitter on the reference clock), whereas a low bandwidth is desired to filter out jitter on the reference clock. Consequently, a compromise is typically required.
The standard for SONET (Synchronous Optical Networks) specifies jitter in three modes: jitter generation, jitter transfer and jitter tolerance. Jitter generation specifications identify how much jitter an interface may add to a data stream, assuming a stable reference clock. Jitter transfer specifications identify how a serial interface must process or filter jitter input from the reference clock, assuming a reference clock derived from a data stream. Jitter tolerance specifications identify how much jitter a serial receiver interface must be able to accept over a link while still recovering data within a bit error rate (BER) limit of the link.
When filtering jitter from a clock derived from a data stream, it is common practice to use a low bandwidth PLL. A frequency source within the low bandwidth PLL is required to have sufficiently low noise. More particularly, a voltage controlled crystal oscillator (VCXO) based PLL is required to meet jitter requirements of common transport protocols (e.g. SONET, Fiber Channel, etc.). The problem with using a VCXO is that the tuning range is very small, usually limited to a few hundred parts per million, and, as a result, different VCXO based PLLs are required in applications with different bit rates.
In the emerging Metropolitan network, there is a need to carry any protocol within existing (e.g. SONET) and emerging (e.g. Optical Network) data transportation facilities. To carry a signal through these networks it is necessary at a receiver to regenerate the data, recover a clock and re-time the data at optical interfaces external to, and within, these networks. There is a need, then, for a receiver that can work with any bit rate, provide compliant level of service, in this case jitter, regenerate a clean clock from a payload asynchronously mapped into a fixed rate carrier and reduce phase noise accumulated through a transmission system to meet jitter requirements.
Currently, PLLs based upon integrated voltage controlled oscillators (VCOs) are used to provide the ability to work with different bit rates, i.e. "bit rate agility". However, because the intrinsic phase noise of these integrated VCO solutions is high, the bandwidth of these PLLs cannot be reduced sufficiently low to filter out accumulated jitter at low frequencies.